1. Field of the Invention
The present invention relates to a semiconductor memory device and a driving method of a semiconductor memory device.
2. Related Art
Recently, following scale-down of elements, development of a full-depletion type floating body cell (FBC) memory (hereinafter, also referred to as “FD-FBC”) is underway. In the FBC memory, each FBC memory stores data “1” or “0” according to an amount of charges stored in a floating body formed on a SOI layer. The FD-FBC differs from a partial-depletion type FBC in that a factor for determining a threshold voltage is not an impurity concentration of a body region but electric field influences of a gate electrode (word line) and a plate electrode on a channel surface. In the FD-FBC, a sufficient potential is applied to the plate electrode, thereby forming a potential well in the body region and storing charges accordingly. Due to this, even if the SOI layer of the FD-FBC is made thin, elements can be scaled down while keeping a threshold voltage difference ΔVth between the memory cell that stores the data “1” and the memory cell that stores the data “0” large.
However, the threshold voltage of the memory cell is increased as the FD-FBC is scaled down for the following reasons. To suppress short channel effect, it is necessary to reduce a thickness of a floating body (a semiconductor layer for forming the body region) as the FD-FBC is scaled down. If the body region is thin, a potential having a large absolute value needs to be applied into the plate region so as to hold the charges in the body region. Accordingly, it is disadvantageously difficult to form an inversion layer on a surface of the body region (channel region), with the result that the threshold voltage of the memory cell is increased.
Further, it is possible that the absolute value of the potential of the plate electrode is increased to increase an amount of signal. If so, the threshold voltage of the memory cell is increased, as well.
If the threshold voltage of the memory cell is increased, it is necessary to apply a high word-line voltage during data writing. In a case that an nMOSFET is employed as the memory cell, for example, the threshold voltage of the memory cell that stores the data “0” is particularly increased. In order to write the data “1” to the memory cell that stores the data “0”, the potential of the word line is required to be increased so as to be able to form a channel in the memory cell that stores the data “0” having the high threshold voltage. This is because it is necessary to cause impact ionization in the memory cell that stores the data “0”.
When the potential of the word line is high, the word line potential may possibly exceed a breakdown voltage of MOSFETs on peripheral circuits such as a row decoder and a word line driving-circuit. A MOSFET formed on an SOI substrate, in particular, is lower in breakdown voltage of the drain than a MOSFET formed on a bulk substrate. As a result, there is a disadvantage that the peripherals are broken down and the semiconductor memory device does not appropriately operate.
When the potential of the word line is increased, a leak current from a drain is increased. This may possibly deteriorate cutoff characteristics. As a result, the leak current flowing in a standby state of the semiconductor memory device is disadvantageously increased.